Introduction to FPGA and RTL Design (Verilog/VHDL) is a hands-on beginner track covering 42 lessons across roughly 18 hours. You build as you go: every module ends in something you can simulate, run on hardware, or put on a resume. No prior hardware background is assumed beyond the prerequisites listed in Module 1.
My synthesis run keeps inferring a latch on the address decoder. I have a default in the case statement — what else causes this?
A default covers the case arms, but every output assigned inside the block needs a value on every path. Assign all of them at the top of the always block, then override.
This bit me last week too. Default-assign everything first, fixed it instantly.
Is there a reason we use non-blocking assignments in sequential blocks but blocking in combinational ones? The lecture said 'convention' but it feels like more than that.
It is more than convention — it is about simulation ordering. Non-blocking makes all sequential updates happen at the same instant, which is what real flip-flops do. Blocking in a combinational block reads like the dataflow it describes.
What board is everyone using? Trying to decide between the Basys 3 and something with more BRAM for the IoT track.
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