eBook Library

The mental model: how your Verilog becomes gates, and what the toolchain does in between.

Pipelines, handshakes, FIFOs and state machines — the shapes that show up in every design.

Self-checking testbenches, coverage, and knowing when a design is actually done.

Reading a timing report without panicking, and the fixes that actually move the number.

Soft cores, peripherals and getting sensor data off the board and onto a network.

The questions that actually get asked, and how to answer them at a whiteboard.