Course: All courses
Syntax, operators, blocking vs non-blocking, and the synthesis subset on two pages.
PDF · 1.4 MB · updated 12 Jul 2026
What an FPGA actually is: LUTs, flip-flops, routing fabric and the toolchain.
Slides · 6.2 MB · updated 10 Jul 2026
Constraint file, top-level module and a testbench you can simulate immediately.
Code · 312 KB · updated 08 Jul 2026
Bank layout, I/O standards and clocking resources for the board used in class.
Datasheet · 3.8 MB · updated 02 Jul 2026
Self-checking testbenches, clock generation and assertion basics in 40 minutes.
Video · 184 MB · updated 28 Jun 2026
create_clock, set_input_delay and the false-path traps that cost you a night.
PDF · 820 KB · updated 24 Jun 2026
Agent, driver, monitor and scoreboard wired up and ready to extend.
Code · 540 KB · updated 19 Jun 2026
Read and write channel timing diagrams with the common deadlock mistakes.
Slides · 4.1 MB · updated 15 Jun 2026
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